![]() ![]() For the single port configuration, you can either read or write data on Port A, you can’t do both at the same time. This would involve driving Wr En high for one clock cycle and Wr Data would have your write data. There might be an application where you want to write some data into the Block RAM buffer, then read it out at a later time. So if your Block RAM is 1024 values deep, it will take at least 1024 clock cycles to read the entire thing out. Note that you can only read one Rd Data value per clock cycle. Read values come out on Rd Data, this is the data stored in the BRAM. Data will be read out on the positive edge of the clock cycle at the address specified by Addr as long as Wr En signal is not active. The way they work is all based on a Clock. ![]()
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